CO-Grand Test 1-Q13

Question

Consider the following instruction sequence for a hypothetical RISC processor.

                                        

                                        

                                        

                                       

                                       

                                       

                                       

Which of the following is a possible legal execution order for this instruction on an out-of-order processor without register renaming?

 

Answer 1

(A)

    Here is a dependency between U and X so there must be 2 stall

    Here is a dependency between V and W so there must be 2 stall

(B)

    Here is a dependency between U and X so there must be 2 stall

   Dependency between V and W there is one stall

(C)

  Here is a dependency between V and U so 2 stalls

   Here is a dependency between U and X so 2 stalls 

  Here is a dependency between X and Y so 1 stall

(D)

   Dependency between T and Y so 1 stall

     

       

 

   

So from all of them, answer should be D because of less number of stalls        

Answer 2

Y is not there in test time.

Comments

Giving marks for all, for ranking, will put the right choice later