CO-Pipelining-Q15

+1 vote

Consider executing the code given below on the pipelined datapath

ADDI R1, R1,4
LOAD R2,100(R1)
ADD R3, R4, R5
LOAD R6,100(R1)
OR R7, R3, R6

How many cycles will it take to execute this code when no data forwarding is used.

asked Jun 12 in Computer Organization by gbmentor (7,990 points)
reshown Jun 13 by gbmentor

4 Answers

0 votes
 
Best answer

When Read and Write in the same clock - 13

Reference: https://courses.cs.washington.edu/courses/cse410/05sp/lectures/cse410-10-pipelining-a.pdf

It will take 13 cycles to execute

answered 5 days ago by 23rishiyadavpro20 (4,120 points)
edited 3 days ago by 23rishiyadavpro20
Even when no data forwarding is mentioned we can consider the split phase between WB-ID?
One more thing
In I2 we are considering ID below WB because content is already available in MA buffer but why we can't consider ID below WB in I5?
Bro I am getting 15 as the answer. Can you explain how in I2 we are considering ID below WB
Sir why i5 is not decoding the instruction ,when i4 is writing the data in registerfile ? Since both task can be performed in the same cycle
I think answer would be 14 only because you have not taken MA stage in I2 instruction
What will be the answer if we consider  Operand forwarding? Is it 10 cycles?
corrected....
When forwarding then 10
0 votes
11  clock cycle
answered 6 days ago by tsnikhilsharmagate2018 (7,480 points)
15 clock cycle m getting
can anyone share the solution
0 votes
When the number of stages in a pipeline aren't given, why do we assume it to be 5?

Suppose if there are only 4 stages(Fetch, Decode, Execte and Write), then the answer will be different.
answered 5 days ago by tsjeganbalajibs (210 points)
Because when nothing is mentioned then classic RISC pipeline is assumed otherwise given in the question

https://en.wikipedia.org/wiki/Classic_RISC_pipeline
0 votes
I still believe that the answer should be 15. @getgatebook can u explain??

My main issue here is that instruction 2 is finished after 8 cycles in the answer selected whereas it should be finsihed after 9 cycles according to me.

There is no such line saying that WB stage is broken into  register read and write.
answered 4 days ago by tssharmaayush361 (270 points)
Reading in decode and writing of write back are not overlapped then there will be many stalls and it is not going to be idle pipeline design. We can always assume that the stages would overlap.
Sir then why have we not used the same concept in between instruction 4 and instruction 5.
How stalls did when Add type of instruction and when load use type of instruction
Refer this https://courses.cs.washington.edu/courses/cse410/05sp/lectures/cse410-10-pipelining-a.pdf

You will get a clear idea for this

as well as there is a question like this on gateoverflow

https://gateoverflow.in/29411/total-cycles-executing-instructions-pipelined-architecture
We should use same idea every where. The correct answer is 13.
@tssharmaayush361 15 is right when WB and Decode can't overlap
see this : http://thegatebook.in/qa/4504/co-pipelining-q6?show=4643#a4643
Answer:
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