In a certain pipelined processor a branch can cause 2 stalls if it is not dealt properly. We can avoid this penalty if a clever compiler can fill the immediate next 2 slots with independent instructions.
Two compilers X and Y generate code for this processor.
Compiler A can fill the first delay slot 35 % of the time and second delay slot 85 % of the time.
Compiler B can fill the first delay slot 20 % of the time and second delay slot 100 % of the time.
Assume that 30 % of the instructions are branch instructions. What is the % of the improvement in CPI(Clocks Per Instruction) with compiler X over compiler Y?