CO-Pipelining-Q14

In a certain pipelined processor a branch can cause 2 stalls if it is not dealt properly. We can avoid this penalty if a clever compiler can fill the immediate next 2 slots with independent instructions.
Two compilers X and Y generate code for this processor.
Compiler A can fill the first delay slot 35 % of the time and second delay slot 85 % of the time.
Compiler B can fill the first delay slot 20 % of the time and second delay slot 100 % of the time.

Assume that 30 % of the instructions are branch instructions.  What is the % of the improvement in CPI(Clocks Per Instruction) with compiler X over compiler Y?

(A) 0

(B) 5

(C) 10

(D) 15

reshown Jun 13

+1 vote

Compiler X  :  $0.70(1)+0.3\{(0.35+0.85)(1)+(0.65+0.15)(1+2))\} = 1.78$

Compiler Y :   $0.70(1)+0.3\{(0.2+1.0)(1)+(0.8)(1+2))\} = 1.78$

Now we can see,

There is no improvement so Option A

answered Jun 14 by (6,590 points)
selected Jun 15
i marked A, but answer key shows@. no marks alotted
if delay slots are not filled properely then penalty is of 2 stalls am i right
yes @surbhipro