CO-Pipelining-Q10

0 votes

P and NP are two architectures and P represents pipeline and NP represents non-pipeline. P has 5 stages, each one has 5 units delay, with interstage buffers of 1 unit delay. NP has 5 stages, each stage has 5 units delay and zero buffering delays. I is an instruction supported by both architectures.
t1= Instruction execution of I in P
t2=Instruction execution time of I in NP
Assume that there are no other delays and stalls except the delays caused by pipelining.

Which one of the following is true?
(A) t1 > t2 in all the cases
(B) t1 < t2 in all the cases
(C) t1< t2 in some cases but not all cases
(D) t1 > t2 in some cases but not all cases

asked 6 days ago in Computer Organization by gbmentor (6,810 points)
reshown 6 days ago by gbmentor

3 Answers

+1 vote
A is correct one
answered 5 days ago by tsnikhilsharmagate2018 (5,940 points)
Please provide some explanation?
+2 votes

@getgatebook

@23rishiyadavpro20

Please help me out on this query.

This is what I know and according to that answer should be T1=T2 but facing difficulty because in this question buffer delays are also given.

 1 . When pipeline stages are perfectly balanced (uniform delay) then one task exec time in the pipeline is also equal to one task exec time in the non pipeline.

2.  When pipeline stages are perfectly balanced (uniform delay) then one task exec time in the non-pipeline is also equal to # of stages in the pipeline.

EG: K=4 N=1 tp=2ns

ET(pipe)=(K+N-1)*tp=8ns

ET(non-pipe)=2+2+2+2=8ns

So i need to ask when buffer delays are considered we have to treat delays of pipeline stages as not perfectly balanced?

answered 4 days ago by tskushagra-guptacse (8,650 points)
1. I think is correct when buffer not included
2. When uniform delay and buffer not included, Reference:https://bit.ly/2FbN6ue
and for your question:

In perfectly balanced pipeline depth = Clock cycle unpipelined / clock cycle pipe

I think interstage delay should not be included

Refer: C-12,13 of  Hannessy and Patterson A Quantitative Approach 5th edition
suppose 5 stages and stage delay of pipeline = 5nsec and delay = 1nsec then clock cycle of pipeline = 6nsec so clock cycle of unpipelined acc to perfectly balanced is 30 nsec but it should be (5+5+5+5+5)nsec = 25 nsec so when interstage delay then not perfect
but answer first should be true only for first instruction for remaining instruction pipeline time should be less than non pipeline time should not answer be c correct if i am wrong
Yes, what you are saying is right but read the question properly "I is an instruction supported by both architectures." here single instruction is taken so C is wrong
Thanks for the explanation. Just little clarification.
1. In order to make T1=T2 either the buffer should not be given in the question or we should avoid it?
2. In perfectly balanced pipeline depth = Clock cycle unpipelined / clock cycle pipe
What does this mean not able to understand.
3. I think interstage delay should not be included
You wrote this in order to make pipeline balanced?
4. Please provide me a link of hannessy because the one i am having has only 6 chapters
http://uni-site.ir/khuelec/wp-content/uploads/Computer-Architecture-A-Quantitative-Approach.pdf
5. In the second comment why you wrote nonpipelined time as 30ns. This indicating what ?

Please clarify these points.
This is the book but pipelining is there in the appendix so C-12, C-13 page no but in your book, 659-660 first go through it then ask...
Sorry for the inconvenience. Understood what you are trying to explain.
Just thought of C-12 ,13 as indexing of appendix C as it contains till C-10 that's why unable to find and got confused.

One more help
It will be good to read the chapters 1-6 (hennessy) or should read the appendix A,B,C or Both. Please help me out as don't want to go through the  complete book.
And any review regarding William stallings CO?
0 votes

Here we have to see carefully "I is an instruction supported by both architectures." It means I is a single instruction

so 

if unit delay = d and k=5 stages and clock cycle = (d+1)

t1 = (5+(n-1))(d+1) for n=1 ,t1 = 5(d+1)

t2 = (d+d+d+d+d) = 5d

so Option A 

if more than 1 instructions then C 

and why A why not D bcz t1 contains buffer 

 

answered 3 days ago by 23rishiyadavpro20 (3,940 points)
edited 3 days ago by 23rishiyadavpro20
Answer:
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