CO-Pipelining-Q7

+2 votes

An instruction pipeline consists of 5 stages Instruction Fetch (IF), Instruction Decode (ID), EX(Execute), Memory(MEM), and Register Write (RW). The following table represents required clock cycles for each instruction at each stage.

No of cycles required :

Instruction IF ID EX MEM RW
1 1 2 1 2 1
2 2 3 2 1 1
3 1 2 1 3 2
4 2 1 2 2 2

The number of clock cycles required is ---?

asked Jun 12 in Computer Organization by gbmentor (63,050 points)
reshown Jun 13 by gbmentor

2 Answers

+1 vote
 
Best answer

16 is the answer. 

answered Jun 13 by getgatebook (31,290 points)
0 votes
16 clock cycle needed
answered Jun 13 by tsnikhilsharmagate2018 (23,380 points)
Answer:
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