CO-Pipelining-Q6

0 votes

NOP instruction is a special instruction which doesn’t perform any operation in its execution phase. Consider the following sets of instructions which are generated by a compiler.

S1:

     https://lh6.googleusercontent.com/SN86srYl5cAk7XjYqh-eEvIFjfe-Mbu-Ww2DSWBdav2bIkrzkStIn_8XKzuv7tA1F92Bv1kD5X6SzNbMDJfgYuIRlayrGl0ncdtMRHsbeXfkqYRFpDlvXLJI3ywySh9J9U3qdsje
         S2:

  https://lh5.googleusercontent.com/mFQwIU2Z8QURPbR3lsZuKjYUnqavXrJ_QpcDoXh4JhTWWKX_2puoI1hGJZL27I9xy6CCDpIJt6y8mhPqQS8NUUUw-sV0BUs3tEV4xJkGkbNhj2fobA0DWEWX9iaAfiXA-dr-4dzu

Assume a 5-stage pipeline with following stages

Instruction Fetch (IF), Instruction Decode (ID), EX(Execute), Memory(MEM), and Register Write (RW).
If each stage takes 2nsec time, The time required to execute S1 minus the time required to execute S2(in nano secs). Assume that there is no data forwarding support from the hardware.

asked 6 days ago in Computer Organization by gbmentor (6,810 points)
reshown 6 days ago by gbmentor

4 Answers

0 votes
 
Best answer

From Hamacher
WB 
stage and Decode stage can not overlap when there is a data dependecy (RAW ).
With that assumption if you solve this question then answer will be 0. 

From Patterson 

WB stage and Decode stage can overlap if there is is a data dependecy (RAW ).

With this assumption if we solve the problem then answer is 2 nsec. 

I feel the second approach is preferred as it optimizes the pipeline performance. 

In the exam based on the answers we need to go. If the question is numerical then preffered approach is the second one. 






 

answered 2 days ago by getgatebook (22,080 points)
0 votes
0 is correct one
answered 5 days ago by tsnikhilsharmagate2018 (5,940 points)
can you share the solution
Please provide explanation. How come answer is zero?
the answer should be 2
0 votes

S1 can be executed like

IF ID EX M WB        
  -              
    -            
      -          
        IF ID EX M WB

So total 9 clock cycle.

S2 will be executed like

IF ID EX M WB      
  --- --- IF ID EX M WB

Here S2 take 8 clock cycle. So difference of 1clock cycle i.e 2nsec.

Here also no data forwarding is used. Only it is taken that WB stage and ID stage is happening at a time. In the 1st half of the clock cylce WB and then in the 2nd half ID (as taught in the lectures.)

So why answer is 0 i.e WB and ID are happening in two different stages. @gatebook

answered 4 days ago by sudiptasenpro (230 points)
I think you are right
first will take 9 clock cycles right in second it will take 9 clock cycles as data forwarding is not supported therefore answer comes out to be zero ID and WB can not occur within same cycle as data forwarding is not supported so zero is correct answer
@surbhipro19 please check what is forwarding here http://web.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/forward.html
Sudipta, check my answer.
0 votes

S1 = 9X2 = 18ns , S2 = 8X2 = 16ns

S1-S2 = 2nsec

 

answered 2 days ago by 23rishiyadavpro20 (3,940 points)
Answer:
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