Rt denotes destination register and Rs denotes source register.
An instruction pipeline consists of 5 stages Instruction Fetch(IF), Instruction Decode(ID), Execute(EX), Memory(MEM) and Register Write(RW).
Which of the following hazard is detected by the above code fragment?
(A) Control hazard
(B) Data hazard
(C) Structural hazard
(D) Reordering hazard