CO-Pipelining-Q4

+2 votes

Rt denotes destination register and Rs denotes source register.
 

https://lh3.googleusercontent.com/1y9WpIXtoW2n2jsf8OounkyfakdBJkf8X4JEaMuUpR_YeI2akmmR2T_pock16pvVZOlobgdghwXJWyPtaEOMbfCL6DxuWwhC8xx4purtZosbctTQmkiUsqM271EJ6x5UrPGnjyky

 

An instruction pipeline consists of 5 stages Instruction Fetch(IF), Instruction Decode(ID), Execute(EX), Memory(MEM) and Register Write(RW).

Which of the following hazard is detected by the above code fragment?

(A) Control hazard

(B) Data hazard

(C) Structural hazard

(D) Reordering hazard

asked Jun 12 in Computer Organization by gbmentor (54,290 points)
reshown Jun 13 by gbmentor

2 Answers

0 votes
 
Best answer
Data hazard is the correct answer.

If there is a  memory read and the destination register is used either as source or destination by next instruction then it will be detected by this code.
This is detecting data hazard.
answered Jun 13 by getgatebook (31,090 points)
selected Jun 13 by getgatebook
0 votes
I think b but not sure
answered Jun 13 by tsnikhilsharmagate2018 (19,690 points)
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