Control Unit - Q3

+2 votes

Following a set of operations describe the Fetch cycle of the Instruction execution.

MAR\leftarrow (PC)

MDR\leftarrow Memory

PC\leftarrow (PC)+1

IR \leftarrow (MDR)

Each micro-operation takes 1-time unit then minimum no of time units required to complete the fetch cycle is?

asked Jun 8 in Computer Organization by gbmentor (54,290 points)
reshown Jun 9 by gbmentor

2 Answers

+1 vote

\\ T1: MAR\leftarrow PC\\ \\T2: MDR\leftarrow Memory\ \mathbf{(System Bus)}\\ PC\leftarrow PC+1\ \mathbf{(Local Bus)}\\ \\T3: IR\leftarrow MDR


Therefore ans should be 3

answered Jun 9 by tskushagra-guptacse (11,400 points)
how u got 3??
T1: PC(out) , MAR(in). Since system bus has been used you can't perform any other operation
T2: Both operations are on different bus as written above. So we can easily perform both operations at the same time. But you can't perform third operation at this time because of the same reason that i have written in T1.
T3: This is the last operation you can easily perform it without any problem.
0 votes
3 cycle required
answered Jun 9 by tsnikhilsharmagate2018 (19,690 points)