Consider the following PC-relative addressing mode instruction of RISC instruction set architecture.
1000: BEQ R1, R2, label
1004: ADD R1, R2, R3
Where the label is used as an offset and 1000 is the memory location from where instruction I1 is fetched. R1, R2, and R3 are general purpose registers.
If R1 = 0; R2=0 and label = 20, what is the memory address of the next instruction to be executed?