In many Architectures which implement the execution of Instruction in five or more stages, decode the instruction and read the source registers at the same time in the same cycle. Though without decoding the instruction it would be difficult to know what registers to be read, still we can do decoding the instruction and reading registers at the same time.
Which one of the following could be the reason to achieve the discussed above?
(A) Using RISC instruction instead of CISC
(B) Using CISC instruction instead of RISC
(C) Source register addresses are represented at same positions in all instructions
(D) By maintaining the multiple decoder circuits