# Addressing Modes- Q10

+1 vote

A computer has following ISA and description:
LOAD and STORE instructions capable of storing data from accumulator to memory locations with indirect mode taking argument as a register
MOV capable of copying data from one reg to another
ADD and SUB capable of adding contents of argument reg to accumulator
LI stores a given 7 bit argument to accumulator
3 Different unconditional branch instructions taking 5 bit offset

Min # of bits required to encode all the instructions above ? asked Jun 4
reshown Jun 5

Total number of registers  = 4
# of bits required = 2

Going by a greedy approach......

LI: 1 bit for opcode and 7 bits for argument to acumulator means total  bits for this instruction minimum. Now we have to manage every other instruction in 8 bits somehow.

Therefore LI instruction encoding starts with 1 bit (say 0)

All other instructions will now start with 1

For 3 branch instructions encoding will be:

1, 1, 1 in addition with 5 bit offset. We are now left with 1 as starting encoding for all other instructions.

MOV instruction will have encoding of 0 as starting and in addition with 2+2 bits for registers

Remaining instructions are

Store Ri

Sub Ri

all these instructions are take 2 bits for operand ==> Reserve at LSB bits.

remaining size we have = first 4 bits fixed from MSB and Last 2 bits fixed ==> in the middle, we have 2 bits remaining

we have 4 instructions ( i.e., Load,Store,Add,Sub ), which requires 2 Bits ==> fix them

01 ---> SUB

11 ---> Store

And hence all encoding done. Total bits required = 8 answered Jun 5 by (2,940 points)
How total # of registers=4?
And sorry but still facing difficulty to understand the answer. Can you explain in some other way.
yes i have the same doubt
ISI 2011 cs problem but not given complete data in problem in realy problem mention no of register 4
Search on Google isi2011-cs-6a problem
For real problem.
Assume a machine has 4 registers (one of which is the accumulator A) and the following instruction set.

LOAD and STORE are indirect memory operations that load and store, using the address stored in the given register operand. Thus, LOADR loads the contents of memory[R] into A, and STORER stores the contents of A in memory[R].
MOV copies any register into any other register.
ADD and SUB operate on the accumulator and one other register, such that A=AopR.
LDC stores a given 7-bit constant in the accumulator.
BRA, BZ, and BNE are branch instructions, each taking a 5-bit offset.
Design an instruction encoding scheme that allows each of the above instructions (along with operands) to be encoded in 8 bits.
Yes you are right. Question is wrong. Thanks for the information brother.
@getbook

Does encode all instruction mean no of bits required for opcode ??? answered Jun 5 by (1,720 points)
Not understand questions properly please provide solutions of that problem. answered Jun 5 by (19,690 points)
@getgatebook

@gbmentor

@vinayakjhapro 18

How used 4 registers where mention in problem please reply? answered Jun 8 by (19,690 points) answered Jun 8 by (19,690 points)