THE GATEBOOK

Normalization Lectures

A typical 4-bit unsigned number multiplier (array multiplier)implementation is given. Assume that Full adder has 2 gate delay. The worst case signal propagation delay or the delay to get P7 in terms of number of gates ?

(A) 20 (B)21 (C)17 (D)19

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@getgatebook

Sir see question number 6.12. Why we can't prove using this for the above question. Please explain.