CO-Basics and ALU-Q11

+1 vote


A typical 4-bit unsigned number multiplier (array multiplier)implementation is given.
Assume that Full adder has 2 gate delay. The  worst case signal propagation delay or the delay to get P7 in terms of number of gates ?

(A) 20

asked Jun 2 in Computer Organization by gbmentor (7,990 points)
edited Jun 5 by getgatebook

3 Answers

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Best answer
answered Jun 5 by getgatebook (22,170 points)
selected Jun 5 by getgatebook
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@getgatebook @gbmentor

Sir how come answer is 20? Please explain.
answered Jun 3 by tskushagra-guptacse (8,720 points)
Sure. We will explain you.
To get P0, we need to wait for 2 delays.
Then to get P1, we need to wait for total 6 delays.
To get P2, wait for total 10 delays.
P6 and P7->20
Sir as told by @akashsaha this might be the correct approach but in Carl hamacher why it is written that the path has a total of 6(n-1)-1 gate delays.
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Sir see question number 6.12. Why we can't prove using this for the above question. Please explain.

answered Jun 3 by tskushagra-guptacse (8,720 points)
In the question they have not used full adders in the first level as they are needed. But in our question we need to use full adders in every level as in the picture we have  full adders in every level.
Okay. Thank you Sir.
But one more thing even they have not considered the first row, then how come  answer would be an odd number of delays as given by this expression 6(n-1)-1. The expression should be such that it produces even delay like we got in this question.