clock frequency = 4GHz hence clock delay is 1/4 * 10 ^(-9) sec or 0.25 nsec

The synchronous counter will be reset when the input will be or

Hence, the sequence will be 0-1-2-3-4-5 or 6 statesNow, the NAND gate latency is 1 nsec and during this 1 nsec the counter will count 3 more times as clock frequency is 0.25 nsec

Counter will count till 1000. So the modulus of the counter is 9.

Option C is the answer.