Digital Counters - 14

+5 votes

Consider the below circuit. Delay of the bubbled NAND gates is 1nsec. Assume that the delay of the counter is zero.

If the clock frequency is 4GHz, then the counter behaves as -

(A) mod - 5 counter

(B) mod - 7 counter

(C) mod - 9 coutner

(D) mod - 10 counter

asked May 22, 2019 in Digital by gbmentor (90,880 points)
reshown May 23, 2019 by gbmentor

2 Answers

+4 votes
 
Best answer

clock frequency  = 4GHz hence clock delay is 1/4 * 10 ^(-9) sec or 0.25 nsec

The synchronous counter will be reset when the input will be 0101_{2} or 5_{10}

Hence, the sequence will be 0-1-2-3-4-5 or 6 statesNow, the NAND gate latency is 1 nsec and during this 1 nsec the counter will count 3 more times as clock frequency is 0.25 nsec

Counter will count till 1000. So the modulus of the counter is 9. 

Option C is the answer. 

 

 

answered May 23, 2019 by getgatebook (34,830 points)
edited May 24, 2019 by getgatebook
In Sol **Hence, additional 4 counting states**.
Sir Please Explain more clearly Why additional 4 states.
Also As Soon as 0101 would be o/p then  Counter would Reset
Then 0101 can never be Seen as an O/P State
(ASYNCHRONOUS RESET)
Then Seq Seen would be 0-1-2-3-4-0    ie 5 states
What is Wrong in above Reasoning?
Please go through the answer now and let me know if you don't understand some thing.
Understood Completely
Thank you Sir!
@akshaypro19 why we are starting from 0101 ?I am not getting @getgatebook
Sir, as it is a NAND gate, so i think the output of it will always be 1 except the combination 0101. Then reset will triggered always except 0101. Please clear my doubt.
@getgatebook
Sir if we consider  NAND gate delay as neglible then what would be the answer to this question? Is it MOD-6 counter as we are dealing with synchronous counter. And if the counter gets changed to Asynchronous counter then answer would be MOD-5 counter?
@kabbujoshipro20
You can start with 0 also but in order to show the increment in the mod value of the counter because of the delay caused by Nand gate we are starting with 5 because this is the value which is going to reset the counter.
is this answer irrespective of the clear input being synchronous or asynchronous with the clock pulse?
Nice explanation sir,
0000 - Counter starts
0001
0010
0011
0100
0101 - soon will be converted to 1111 before NAND and NAND will initiate reset (0000) so ideally after 0100 it should be 0000 but NAND is slower than cycle thus counter will keep moving ahead with counting as there no one to reset it.
0101 - will keep moving from here, consider it as part of counter state
0110
0111
1000 - Here now NAND will produce 0 and NOT before Counter will give 1 to RESET and counter will reset. so total 9 states by counter thus Mod 9.
It is (reset)' right?? o/p of NAND is zero and then one bubble will make it 1. So 1 will be passed to (Reset)'.Then Reset will be zero???Plz help
+2 votes
Explaination-

Normally this counter will count 5 states from 0000 to 0100 [5] and on input 0101 (5) it will reset.

But Nand gate has 1 ns delay. So when Nand output is avaiable then only counter will be reset untill it will go on couting. Now clock time will be 1/4*10^-9= 0.25ns.

means at every .25 ns counter will count and update its state. But nand has delay of 1ns so untill nand output will be available counter will be counting 1/.25=4 states. Therefore total counted states are 5+4=9. And just after this, nand output is available and it will reset the counter to 0000.

Hence MOD-9 counter.
answered Aug 7, 2019 by bhargavakapilpro20 (14,660 points)
Answer:
...