THE GATEBOOK

Normalization Lectures

Consider the below circuit. Delay of the bubbled NAND gates is 1nsec. Assume that the delay of the counter is zero.

If the clock frequency is 4GHz, then the counter behaves as -

(A) mod - 5 counter

(B) mod - 7 counter

(C) mod - 9 coutner

(D) mod - 10 counter

clock frequency = 4GHz hence clock delay is 1/4 * 10 ^(-9) sec or 0.25 nsec

The synchronous counter will be reset when the input will be or

Hence, the sequence will be 0-1-2-3-4-5 or 6 statesNow, the NAND gate latency is 1 nsec and during this 1 nsec the counter will count 3 more times as clock frequency is 0.25 nsec

Counter will count till 1000. So the modulus of the counter is 9.

Option C is the answer.