- at 25:52 ?
- Sir was the state minimization table related to the state table of the second flip flop circuit example or it was separately for that state diagram consisting a,b,c,d..etc ?
- at @21:30
- sir regarding edge triggered
- It should be y (xz'--> xy) in place z'?? isn't it?
- Hello sir, While implementing half adder using only NAND Gates I got the result using 7 NAND gates.Is that OK?
- @ 18.00